Reducing or eliminating pre-amorphization in transistor manufacture

ABSTRACT

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/046,147 and now U.S. Pat. No. 8,937,005, which is a continuation ofU.S. application Ser. No. 13/473,403 and now U.S. Pat. No. 8,569,156,which claims the benefit of U.S. Provisional Application No. 61/486,494,each being hereby incorporated by reference herein.

TECHNICAL FIELD

Integrated circuit processes and structures to allow for improvedsemiconductor substrate treatment are disclosed.

BACKGROUND

Placement of dopants in MOSFET transistors is increasingly difficult astransistor size is reduced. Misplaced dopants can reduce transistorperformance and increase transistor variability, including variabilityof channel transconductance, capacitance effects, threshold voltage, andleakage. Such variability increases as transistors are reduced in sizewith each misplaced dopant atom having a greater relative effect ontransistor properties consequent to the overall reduction in number ofdopant atoms. One common source of misplaced dopants occurs as a resultof damage to crystal structure of a transistor during manufacture, whichincreases defect pathways and creates excess silicon interstitials thatallow enhanced dopant movement in undesired regions of the transistor.

A pre-amorphizing implant (PAI) can be used in semiconductor processingas a way to set up for dopant substitutionality. A PAI process generallyinvolves introducing a dopant species using a high energy ionimplantation to impart damage and thereby amorphize the implantedregion. The damage and amorphization are important so that dopants froma previous or subsequent ion implantation can more easily move intosubstitutional sites. If PAI is used, then a subsequent anneal isperformed to render the substrate crystalline again.

However, with the typical anneal process that is used, which is either asolid phase epitaxy (SPE) or high temperature anneal such as RTA, thereremains residual damage from PAI which can create a pathway for leakagecurrent by acting as localized generation/recombination sites.

BRIEF DESCRIPTION OF THE FIGURES

For a more complete understanding of the present disclosure, referenceis made to the following description taken in conjunction with theaccompanying drawings, wherein like reference numerals represent likeparts, in which:

FIG. 1 illustrates an embodiment of an NMOS transistor incorporatinggermanium pre-amorphization implants and a screen layer;

FIG. 2 illustrates an embodiment of a PMOS transistor incorporating ascreen layer and formable along with a structure according to FIG. 1;

FIG. 3 illustrates an embodiment of an NMOS transistor having noincorporated germanium pre-amorphization implants, but with an in-situcarbon doped silicon substrate to limit boron screen diffusion;

FIG. 4 illustrates an embodiment of a PMOS transistor having noincorporated germanium pre-amorphization implants, along with an in-situcarbon doped silicon substrate formable along with a structure inaccordance with FIG. 4;

FIG. 5 illustrates an embodiment of an NMOS transistor having noincorporated germanium pre-amorphization implants, but with an in-situcarbon doped silicon epitaxial layer epitaxially grown above the screen;

FIG. 6 illustrates an embodiment of a PMOS transistor having noincorporated germanium pre-amorphization implants, but with an in-situcarbon doped silicon epitaxial layer formable along with a structure inaccordance with FIG. 5;

FIG. 7 illustrates an embodiment of an NMOS transistor having noincorporated germanium pre-amorphization implants, but with twoseparately formed carbon doped regions to limit boron screen layerdiffusion;

FIG. 8 illustrates an embodiment of an NMOS transistor having noincorporated germanium pre-amorphization implants, but with threeseparately formed carbon doped regions to limit boron screening layerdiffusion;

FIG. 9 illustrates process steps for transistor manufacture that can beused to produce embodiments in accordance with the present disclosure;

FIG. 10 illustrates process steps for transistor manufacture for severalalternative process embodiments that use selective epitaxial layers;

FIG. 11 illustrates process steps for transistor manufacture that can beused to limit the carbon species to the NMOS transistors only.

DETAILED DESCRIPTION

Unwanted transient enhanced diffusion (TED) resulting from defects andinjected silicon interstitials from defect clusters can easily reduce ordestroy transistor functionality, particularly for nanometer scaletransistors having complex dopant profiles such as disclosed, forexample, in embodiments of various transistor structures andmanufacturing processes more completely described in U.S. applicationSer. No. 12/708,497 titled “Electronic Devices and Systems, and Methodsfor Making and Using the Same”, U.S. application Ser. No. 12/971,884titled “Low Power Semiconductor Transistor Structure and Method ofFabrication Thereof”, U.S. application Ser. No. 12/971,955 titled“Transistor with Threshold Voltage Set Notch and Method of FabricationThereof”, and U.S. application Ser. No. 12/895,785 titled “AdvancedTransistors With Threshold Voltage Set Dopant Structures”, thedisclosures of which are hereby incorporated herein by reference intheir entirety.

As shown in FIGS. 1 and 2, a transistor 100 is built on a substrate 102and includes an isolation structure 104, a gate, a gate dielectric 140,source/drain 106, a gate spacer 144 separating the source/drain 106 fromthe gate electrode 142, lightly doped drains (LDD) 108, and asubstantially undoped silicon channel layer 110 that can be epitaxiallygrown/deposited. Typically, the LDD 108 are implanted following theformation of the gate stack, followed by gate spacer 144 formation andthen implant or, alternatively, selective epitaxial deposition of deepsource/drain regions 106. The transistor 100 shown in FIG. 1 is an NMOSdeeply depleted channel (DDC) transistor, while FIG. 2 illustrates acomplementary PMOS DDC transistor 101 supported on the same substrate.Each transistor 100 and 101 has a substantially undoped channel formedin a common blanket epitaxial layer 110, but differing in dopant typesand implant energies. With suitable changes to account for differencesin dopants, structures and processes for the NMOS and PMOS transistors100 and 101 are similar and are discussed together in the followingwhere appropriate.

With reference to FIG. 1, the NMOS transistor 100 includes a screenlayer 120. In certain embodiments, the screen layer 120 is formed byimplanting dopants into a P-well (not shown) formed on the substrate102. In alternative embodiments, the screen layer 120 is formed on theP-well using methods such as in-situ doped epitaxial silicon depositionor epitaxial silicon deposition followed by dopant implantation. Thescreen layer 120 formation step occurs preferably before shallow trenchisolation (STI) formation, but can be implemented after STI. Boron (B),Indium (I), or other P-type materials may be used for P-type screenimplants (as shown with reference to the screen layer 120 in FIG. 1).Arsenic (As), antimony (Sb), phosphorous (P), and other N-type materialscan be used for N-type screen implants (as shown with reference to thescreen layer 120 in FIG. 2). In certain embodiments, the screen layer120 has a dopant concentration between about 1×10¹⁹ to 5×10²⁰ dopantatoms/cm³, with the selected dopant concentration dependent on thedesired threshold voltage as well as other desired transistorcharacteristics.

As shown in FIG. 1, an anti-punchthrough (APT) suppression layer 122 mayoptionally be formed beneath the screen layer 120. The APT suppressionlayer 122 can help reduce junction leakage. The APT suppression layer122 can be separated from the screen layer 120 (e.g., the screen layer120 as shown in FIG. 1) or it may contact the screen layer 120 (e.g.,the screen layer 120 as shown in FIG. 2). Typically, the APT suppressionlayer 122 can be formed by direct implant into a lightly doped well, byout-diffusion from the screening layer 120, in-situ growth, or otherknown process. The APT suppression layer 122 has a dopant concentrationless than the screening layer 120, typically set between about 1×10¹⁷dopant atoms per cm³ and about 1×10¹⁹ dopant atoms per cm³. In addition,the APT suppression layer 122 dopant concentration is set higher thanthe overall dopant concentration of the substrate 102 or the well inwhich the transistor is formed.

In certain embodiments, an optional threshold voltage set layer isformed above the screen layer 120, typically formed as a thin dopedlayer. The threshold voltage set layer can be either adjacent to,incorporated within, or vertically offset from the screen layer 120. Incertain embodiments, the threshold voltage set layer is formed byimplantation prior to the formation of the undoped epitaxial layer 110.In alternative embodiments, the threshold voltage set layer can beformed by way of controlled out-diffusion of dopant material from thescreen layer 120 into an undoped epitaxial layer, controlled in-situdoped epitaxial deposition either as part of screen layer 120 formationor separate from the formation of the screen layer 120, controlledformation before the substantially undoped epitaxial layer 110 isformed, or by implant after the substantially undoped epitaxial layer110 is formed. Setting of the threshold voltage for the transistor isimplemented by suitably selecting dopant concentration and depth of thethreshold voltage set layer as well as maintaining a separation of thethreshold voltage set layer from the gate dielectric 140, leaving asubstantially undoped channel layer 110 directly adjacent to the gatedielectric. In certain embodiments, the threshold voltage set layer hasa dopant concentration between about 1×10¹⁷ dopant atoms/cm³ and about1×10¹⁹ dopant atoms per cm³. In alternative embodiments, the thresholdvoltage set layer has a dopant concentration that is approximately lessthan half of the concentration of dopants in the screen layer 120.

The channel layer 110 contacts and extends between the source/drain 106and supports movement of mobile charge carriers between the source andthe drain. In certain embodiments, the channel layer 110 is formed abovethe screen layer 120 and threshold voltage set layer (the screen layer120, threshold voltage set layer, and APT suppression layer 122 are alsoreferred to as well implant layers) by way of a blanket or selectivesilicon EPI deposition, resulting in an intrinsic substantially undopedchannel layer 110 of a thickness tailored to the technicalspecifications of the device. As a general matter, the thickness of thesubstantially undoped channel layer 110 ranges from approximately 5-30nm, with the selected thickness based upon the desired threshold voltageand other transistor performance metrics for the transistor andtransistor design node (i.e. a 20 nm gate length transistor maytypically have a thinner channel thickness than a 45 nm gate lengthtransistor). Preferably, the substantially undoped channel region 110has a dopant concentration less than 5×10¹⁷ dopant atoms per cm³adjacent or near the gate dielectric 140. In some embodiments, thesubstantially undoped channel layer 110 may have a dopant concentrationthat is specified to be approximately less than one tenth of the dopantconcentration in the screen layer 120. In still other embodiments,depending on the transistor characteristics desired, the substantiallyundoped channel layer 110 may contain dopants so that the dopantconcentration is elevated to above 5×10¹⁷ dopant atoms per cm³ adjacentor near the gate dielectric 140. Preferably, the substantially undopedchannel layer 110 remains substantially undoped by avoiding the use ofhalo or other channel implants. In one embodiment, the channel layer 110is formed by a blanket (or selective) epitaxial deposition step that isperformed after forming the screen layer 120.

The isolation structure 104 of FIGS. 1 and 2 can be formed through STIstructures that are etched and filled with a dielectric material. Incertain embodiments, STI structures are preferably formed after theblanket EPI deposition step, using a process that remains within athermal budget that effectively avoids substantial change to the dopantprofiles of the previously formed screen layer 120 and threshold voltageset layer.

In operation, when gate electrode 142 voltage is applied to thetransistor 100 at a predetermined level, a depletion region formed inthe substantially undoped channel layer 110 may extend to the screenlayer 120. The screen layer 120, if fabricated according tospecification, effectively pins the depletion region to define thedepletion zone depth.

The threshold voltage (Vt) in conventional field effect transistors(FETs) can be set by directly implanting a “threshold voltage implant”into the channel, raising the threshold voltage to an acceptable levelthat reduces transistor off-state leakage while still allowing speedytransistor switching. Alternatively, the threshold voltage inconventional FETs can also be set by a technique variously known as“halo” implants, high angle implants, or pocket implants. Such implantscreate a localized graded dopant distribution near a transistor sourceand drain that extends a distance into the channel. Halo implants areoften required by transistor designers who want to reduce unwantedsource/drain leakage conduction or “punch through” current and othershort channel effects, but have the added advantage of adjusting thethreshold voltage. Unfortunately, halo implants introduce additionalprocess steps, thereby increasing the manufacturing cost. Also, haloimplants can introduce additional dopants in random unwanted locationsin the channel. These additional dopants increase the variability of thethreshold voltage between transistors and decrease mobility and channeltransconductance due to the adverse effects of additional and unwanteddopant scattering centers in the channel. Eliminating or greatlyreducing the halo implants is desirable for reducing manufacture timeand making more reliable wafer processing. By contrast, the techniquesfor forming the transistor 100 use different threshold voltage settingtechniques that do not rely on halo implants (i.e. haloless processing)or channel implants to set the threshold voltage to a desired range. Bymaintaining a substantially undoped channel near the gate, thesetransistors further allow for greater channel mobility for electron andhole carriers with reduced variation in threshold voltage from device todevice.

As will also be appreciated, position, concentration, and thickness ofthe screen layer 120 are important factors in the design of the DDCtransistor 100. In certain embodiments, the screen layer 120 is locatedabove the bottom of the source and drain junctions 106 and below the LDDjunctions 108. To dope the screen layer 120 so as to cause its peakdopant concentration to define the edge of the depletion width when thetransistor is turned on, methods such as delta doping, conventionaldopant implants, or in-situ doping is preferred, since the screen layer120 should have a finite thickness to enable it to adequately screen thewell while avoiding creating a path for excessive junction leakage. Withsuch a screen layer 120, the transistor 100 can simultaneously have goodthreshold voltage matching, low junction leakage, good short channeleffects, and still have an independently controllable body due to astrong body effect. In addition, multiple transistors having differentthreshold voltages can be easily implemented by customizing theposition, thickness, and dopant concentration of the threshold voltageset layer and/or the screen layer 120 while at the same time achieving areduction in the threshold voltage variation. In one embodiment, thescreen layer 120 is positioned such that the top surface of the screenlayer 120 is located approximately at a distance of Lg/1.5 to Lg/5 belowthe gate dielectric 140 (where Lg is the gate length). In oneembodiment, the threshold voltage set layer has a dopant concentrationthat is approximately 1/10 of the screen layer 120 dopant concentration.In certain embodiments, the threshold voltage set layer is thin so thatthe combination of the threshold voltage set layer and the screen layer120 is located approximately within a distance of Lg/1.5 to Lg/5 belowthe gate dielectric 140.

Modifying threshold voltage by use of a threshold voltage set layerpositioned above the screen layer 120 and below the substantiallyundoped channel layer 110 is an alternative technique to conventionalthreshold voltage implants for adjusting threshold voltage. Care must betaken to prevent dopant migration into the substantially undoped channellayer 110, with the use of low temperature anneals and dopantanti-migration techniques being recommended for many applications. Moreinformation about the formation of the threshold voltage set layer isfound in pending U.S. application Ser. No. 12/895,785, the entirety ofwhich is hereby incorporated herein by reference.

Dopant migration resistant implants or layers of carbon,pre-amorphization implants, or the like, can be applied below, alongwith, or above the screen layer 120 to further limit dopant migration.In FIG. 1, the extent of carbon implants is generally indicated toextend through the screen layer 120 and may extend upward through eitherpart of or all of the channel 110. Germanium pre-amorphization implantsare generally indicated to extend from above the NMOS screen layer 120downward past the APT suppression layer 122. For DDC devices thatutilize a pre-amorphization layer and SPE anneal, the screening layer120, the threshold voltage set layer, and the APT suppression layer 120(the screen layer 120, threshold voltage set layer, and APT suppressionlayer 122 are also referred to as well implant layers) can all beaffected by remaining germanium end of range (EOR) damage that caninclude dislocations, high interstitial injection, and other crystaldefects to cause unwanted migration of boron or other dopant atomsthrough the damaged area.

Reducing unwanted damage effects while maintaining desired dopantprofiles is possible with use of the following disclosed structures andprocesses. FIG. 3 generally illustrates a portion of a NMOS transistor200 having a screen layer 220 and a substantially undoped channel layer210 that are similar to corresponding layers of transistor 100 in FIG. 1but formed without the use of Ge PAI. The transistor 200 insteadutilizes in-situ carbon doped silicon substrate in which the wellimplant layers are formed in order to limit NMOS screen layer 220diffusion. The transistor 200 includes an NMOS APT suppression layer222, a NMOS screen layer 220 formed in the carbon doped siliconsubstrate and positioned above the NMOS APT suppression layer 222, and asubstantially undoped channel layer 210. In one embodiment, carbon dopedsilicon is in-situ grown as an epitaxial layer on the substrate forminga carbon doped silicon substrate into which the NMOS screen layer 220dopants are subsequently implanted so as to form the NMOS screen layer220 within the carbon doped silicon substrate. The carbon dopants in thein-situ doped silicon substrate occupy substitutional sites, therebyreducing unwanted diffusion of NMOS screen layer 220 dopants andmaintaining desired dopant profiles. As shown FIG. 3, some carbondopants can diffuse into the substantially undoped channel layer 210during subsequent process steps that form remaining elements of thetransistor 200, e.g. during gate formation and/or source/drain 206formation.

FIG. 4 generally illustrates a portion of the PMOS transistor 201 thatcan be formed on the same substrate as the NMOS transistor 200 depictedin FIG. 3. More specifically, this transistor 201 has added to itsstructure in-situ carbon doped silicon that is grown in the same processsteps as for forming the carbon doped silicon substrate of FIG. 3. Thetransistor 201 includes a PMOS APT suppression layer 222, a PMOS screenlayer 224 formed in the carbon doped silicon substrate and positionedabove the PMOS APT suppression layer 222, and a substantially undopedchannel layer 210. The transistor 201 utilizes the in-situ carbon dopedsilicon substrate to limit PMOS screen layer 220 diffusion. In oneembodiment, the carbon doped silicon for the PMOS transistor 201 can begrown at the same time the carbon doped silicon for NMOS transistor 200and PMOS screen layer 220 is formed, resulting in the carbon dopedsilicon substrate for the PMOS transistor 201. In one embodiment, thecarbon doped silicon is in-situ grown as an epitaxial layer on thesubstrate 202 forming a carbon doped silicon substrate into which thePMOS screen layer 220 dopants are subsequently implanted so as to formthe PMOS screen layer 220 within the carbon doped silicon substrate. Thecarbon dopants in the in-situ carbon doped silicon substrate occupysubstitutional sites, thereby reducing unwanted diffusion of PMOS screenlayer 220 dopants and maintaining desired dopant profiles. As shown inFIG. 4, some carbon dopants can diffuse into the substantially undopedchannel layer 210 during subsequent process steps to form remainingelements of the transistor 201, e.g. gate formation or source/drain 206formation.

The PMOS transistor 201 has carbon dopants in the PMOS screen layer 220because the carbon doped silicon substrate is formed as a blanketepitaxial layer that is formed over both the NMOS and PMOS transistorregions 200 and 201 during the same process step. However, the carbondoping may be eliminated for the PMOS transistors 201 if the PMOS screenlayer 220 is formed using dopants having a low diffusivity such that thediffusion of PMOS screen layer 220 dopant profile can be maintainedwithout using carbon. Not using carbon in such embodiments can beadvantageous because the carbon atoms can result in reduced mobility ofthe charge carriers and, therefore, affect the electricalcharacteristics of the PMOS transistor 201. Therefore, in alternativeembodiments that use selective epitaxial layers to form the PMOS andNMOS screen layers 220, the PMOS transistors 201 can use a slowdiffusing dopant species (such as As or Sb) to form the PMOS screenlayer 220 and not have any carbon, while the NMOS transistors 200 canstill use carbon to reduce the diffusion of NMOS screen layer 220dopants.

FIG. 5 is an illustration of another variation of an NMOS transistor 300having no incorporated germanium pre-amorphization implants, but with anin-situ epitaxial carbon doped silicon layer 330 positioned above theNMOS screen layer 320 to limit the diffusion of dopants from the screenlayer 320. The transistor 300 also includes a NMOS APT suppression layer322 and a NMOS screen layer 320 that are formed in the substrate 302 orin a doped well in the substrate 302. In one embodiment, the carbondoped silicon layer 330 is formed as an in-situ doped blanket epitaxiallayer and is typically a thin layer that is 5-50 nm thick. The carbondopants in the in-situ doped epitaxial layer 330 occupy substitutionalsites, thereby reducing unwanted diffusion of NMOS screen layer 320dopants and maintaining desired dopant profiles. Typically, the carbondoped silicon layer 330 reduces the diffusion of NMOS screen layer 320dopants by protecting the NMOS screen layer 320 from interstitialsgenerated above the NMOS screen layer 320, e.g., at the gate dielectric340. As shown in FIG. 5, the substantially undoped channel layer 310 isformed above the carbon doped silicon layer 330. In one embodiment, thesubstantially undoped channel layer 310 is formed as a blanket epitaxiallayer. In certain embodiments, the thickness of the carbon doped siliconlayer 330 can range from as little as 5 nm up to the full thickness ofthe substantially undoped channel layer 310. In one embodiment, thethickness of the carbon doped silicon layer 330 is selected to besufficient to trap interstitials generated from the gate dielectric 340.

FIG. 6 generally illustrates a portion of the PMOS transistor 301 thatcan be formed on the same substrate as the NMOS transistor 300 depictedin FIG. 5. The transistor 301 includes a PMOS APT suppression layer 322,a PMOS screen layer 320 positioned above the PMOS APT suppression layer322, a carbon doped silicon layer 330 is formed above the NMOS screenlayer 320, and a substantially undoped channel layer 310 formed abovethe carbon doped silicon layer 330. The PMOS APT suppression layer 322,and the PMOS screen layer 320 are formed by implanting dopants in thesubstrate 302 or in a doped well in the substrate 302. The carbon dopedsilicon layer 330 can be formed as a blanket epitaxial layer that isformed over both the NMOS transistor 300 and the PMOS transistor 301during the same process step. The carbon doped silicon layer 330 isformed above the NMOS and PMOS screen layers 320. The carbon dopants inthe in-situ doped epitaxial layer 330 occupy substitutional sites,thereby reducing unwanted diffusion of PMOS screen layer 320 dopants andmaintaining desired dopant profiles. Typically, the carbon doped siliconlayer 330 reduces the diffusion of PMOS screen layer 320 dopants byprotecting the PMOS screen layer 320 from interstitials generated abovethe PMOS screen layer 320, e.g., at the gate dielectric 340. As shown inFIG. 6, the substantially undoped channel layer 310 is formed above thecarbon doped silicon layer 330. In one embodiment, the substantiallyundoped channel layer 310 can also be a blanket epitaxial layer that isformed over both the PMOS transistor 301 and the NMOS transistor 300during the same process steps. In alternative embodiments, where lowdiffusivity dopant species are used to form the PMOS screen layer 320,the carbon doped silicon layer 330 may not be desired. Such alternativeembodiments can use selective epitaxy from the carbon doped siliconlayer 330 above the NMOS screen layer 320 without forming the carbondoped silicon layer 330 above the PMOS screen layer 320, resulting in aPMOS transistor 301 that does not have any carbon dopants.

FIG. 7 is an illustration of an NMOS transistor 400 having noincorporated germanium pre-amorphization implants, but with an in-situepitaxial carbon doped silicon layer 430 positioned above the screenlayer 420 and a deep carbon implant layer 432 positioned below thescreen layer 420 to limit the diffusion of dopants from the screen layer420. The transistor 400 can be formed by implanting a NMOS APTsuppression layer 422 in the substrate 402 or in a doped well in thesubstrate 402. Subsequently, carbon can be implanted to form the deepcarbon implant layer 432, which is followed by an implant step thatforms the NMOS screen layer 420. Since the deep carbon implant layer 432protects the NMOS screen layer 420 from interstitials generated belowthe screen layer 420, it is typically positioned close to the NMOSscreen layer 420. However, it can also be positioned below the NMOSscreen layer 420 (such as between the NMOS screen layer 420 and the NMOSAPT suppression layer 422), below the NMOS APT suppression layer 420, orabove the source of interstitials below the NMOS screen layer 420. Thus,one layer of carbon 430 is an in-situ doped silicon layer epitaxiallygrown above the screen layer 420 and the other layer of carbon 432 is adeep carbon implant layer positioned below the screen layer 420. Thepositioning of deep carbon implant layer 432 in relation to in-situepitaxial carbon doped silicon layer 430 (i.e. the distance betweenthese layers and depth within the substrate 302) may be determined basedon a desired threshold voltage for the NMOS transistor 400. Inalternative embodiments, fluorine can be implanted instead of carbon toform the deep implant layer 432. The use of fluorine instead of carboncan be advantageous because fluorine can be fully activated with anormal spike anneal, while carbon may only be partially activated.

Referring to FIG. 7, the carbon doped silicon layer 430 is formed abovethe NMOS screen layer 420 and a substantially undoped channel layer 410is formed above the carbon doped silicon layer 430. Formation of acomplimentary PMOS transistor, though not shown, may similarly beperformed as PMOS transistors 101, 201, and 301 discussed above with theadditional features as discussed in FIG. 7. In one embodiment, thesubstantially undoped channel layer 410 and/or the carbon doped siliconlayer 430 is formed as a blanket epitaxial layer that is formed overboth a PMOS transistor and NMOS transistors 400 formed on the samesubstrate 402 during the same process steps. Typically, the carbon dopedsilicon layer 430 protects the NMOS screen layer 420 from interstitialsgenerated above the NMOS screen layer 420, e.g., at the gate dielectric440, and the deep carbon implant layer 432 protects the NMOS screenlayer 420 from interstitials generated below the deep carbon implantlayer 432. In one embodiment, where the PMOS screen layer of the PMOStransistor (not shown) is formed using a slow diffusing dopant species,the deep carbon implant layer can be formed only for the NMOS transistor400, and the PMOS transistor may not have a deep carbon implant layerpositioned below the PMOS screen layer. In such embodiments, the carbondoped silicon layer 430 may not be desired for the PMOS transistor.Therefore, the carbon doped silicon layer 430 can be formed as aselective epitaxial layer that is formed only above the NMOS screenlayer 420 and not above the PMOS screen layer, resulting in a PMOStransistor that does not have any carbon dopants. In variousembodiments, only one carbon doped layer (i.e., either the deep carbonimplant layer 432 or the carbon doped silicon layer 430) can be used toprotect the NMOS screen layer 420 or both carbon doped layers can beused (as illustrated in FIG. 7).

FIG. 8 is an illustration of an NMOS transistor 500 having noincorporated germanium pre-amorphization implants, but with a deepin-situ epitaxial carbon doped silicon formed in the substrate 502 toextend throughout the screen layer 520, an in-situ epitaxial carbondoped silicon layer 530 formed between the screen layer 520 and thesubstantially undoped channel 510, and a deep carbon implant layer 532positioned below the screen layer 520 to limit the diffusion of dopantsfrom the screen layer 520. The transistor 500 includes a NMOS APTsuppression layer 522 that is formed by implanting dopants in asubstrate 502 or a doped well in the substrate 502. After forming theNMOS APT suppression layer 522, carbon can be implanted to form the deepcarbon implant layer 532. Thus, one use of carbon is in-situ carbondoped silicon epitaxially grown over the substrate 502 to create acarbon doped substrate region within which the device well implantlayers can be formed. The second use of is a deep carbon implant layer532 positioned below the screen layer 520. The third use of carbon is anin-situ carbon doped silicon layer 530 epitaxially grown above thescreen layer 520. The positioning of deep carbon implant layer 532 inrelation to in-situ epitaxial carbon doped silicon layer 530 (i.e. thedistance between these layers and depth within the substrate 502) may bedetermined based on a desired threshold voltage for the NMOS transistor500. In alternative embodiments, fluorine can be implanted instead ofcarbon to form the deep implant layer 532. In one embodiment, the deepin-situ carbon doped silicon is grown as an epitaxial layer on thesubstrate 502 forming a carbon doped silicon substrate into which theNMOS screen layer 520 dopants are subsequently implanted so as to formthe NMOS screen layer 520 within the carbon doped silicon substrate. Thecarbon dopants in the carbon doped silicon substrate occupysubstitutional sites, thereby reducing unwanted diffusion of NMOS screenlayer 520 dopants and maintaining desired dopant profiles. The thincarbon doped silicon layer 530 is formed above the NMOS screen layer anda substantially undoped channel layer 510 is formed above the carbondoped silicon layer 530. In one embodiment, the substantially undopedchannel layer 510 and/or the carbon doped silicon layer 530 can beformed as a blanket epitaxial layer that is formed over both a PMOStransistor (not shown) and NMOS transistor 500 formed on the samesubstrate 502 during the same process steps. In one embodiment, wherethe PMOS screen layer of the PMOS transistor is formed using a slowdiffusing dopant species, the deep carbon implant layer can be formedonly for the NMOS transistor 500, and the PMOS transistor may not have adeep carbon implant layer positioned below the PMOS screen layer. Insuch embodiments, the carbon doped silicon layer 530 and the carbondoped silicon substrate may not be desired for the PMOS transistor.Therefore, the carbon doped silicon layer 530 and the carbon dopedsilicon substrate can be formed as selective epitaxial layers that areformed only for the NMOS transistor 500 and not for the PMOS transistor,resulting in PMOS transistors that do not have any carbon dopants.

FIG. 9 illustrates several embodiments of a process 900 that can be usedto produce structures of the present disclosure. As shown in step 905,carbon doped silicon can be in-situ grown as an epitaxial layer, forminga carbon doped silicon substrate area into which the DDC transistor cansubsequently be fabricated. Embodiments of DDC transistors that areformed in a carbon doped substrate area have been described previouslywith reference to FIGS. 3, 4, and 8. In one embodiment, the in-situcarbon doped silicon can be grown on single wafers using chemical vapordeposition at temperatures in the range of 550° C.-800° C. and pressuresin the range of 10-400 torr (T), at atmospheric pressure, or in a systempressurized to exceed atmospheric pressure, using a H₂ carrier gas inthe range of 20-40 standard liters per minute (slm) with a siliconsource such as SiH₄ or Si₂H₆ in the range of 50-100 standard cubiccentimeter per minute (sccm) and a carbon source such as CH SiH₃ or C₂H₄in the range of 10-50 sccm, where the mole fraction of the carbon sourcein H₂ can be in the range of 0.1% to 1%). In an alternative embodiment,the in-situ carbon doped silicon can be grown in a batch UHVCD furnaceat 450-750° C. and 1-100 mT temperature and pressure, respectively,using an ambient such as He, H2, N2, or Ar. The silicon source can beSiH₄ or Si₂H₆ in the range of 1-50 sccm and the carbon source can be CHSiH₃ or C₂H₄ in the range of 1-10 sccm, where the mole fraction of thecarbon source in H₂ can be in the range of 0.01% to 1%). In certainembodiments, the thickness of the in-situ carbon doped silicon can rangebetween 20-100 nm. Typically the thickness of the in-situ carbon dopedsilicon is selected to be greater than the thickness of the PMOS screenlayer to be formed, so that the PMOS screen layer is formed entirelywithin the in-situ carbon doped silicon. For example, if the PMOS screenlayer thickness is 30 nm, the thickness of the carbon doped silicon canbe selected to be 40 nm.

In step 910, a PMOS mask is photolithographically patterned on a wafer,which is then used in step 915 to form the PMOS well. In one embodiment,phosphorus (P) is implanted at 200-400 keV and at doses in the range of1×10¹³ to 5×10¹³ atoms/cm² to form the PMOS well. In steps 920 and 925,respectively, the PMOS APT suppression layer and the PMOS screen layerare formed. The PMOS well implant and/or the PMOS APT suppression layerimplant can be done either directly into the in-situ carbon dopedsilicon or it can be directed to form a doped region below the in-situcarbon doped silicon. However, the PMOS screen implant is done directlyinto the in-situ carbon doped silicon layer so that the PMOS screenlayer is formed within this substrate region. In one embodiment, arsenic(As) is implanted at 50-200 keV at doses in the range of 5×10¹² to5×10¹³ atoms/cm² to form the PMOS APT suppression layer and antimony(Sb) is implanted at 10-50 keV at doses in the range of 5×10¹² to 5×10¹³atoms/cm² to form the PMOS screen layer. The PMOS mask is removed atstep 930 and an NMOS mask is formed at step 935. In step 940, the NMOSmask is used to form the NMOS well. In one embodiment, boron (B) isimplanted at approximately 100-250 keV, at doses in the range of 1×10¹³to 5×10¹³ atoms/cm² to form the NMOS well. In step 945, the NMOS APTsuppression layer is implanted in the NMOS well. In one embodimentadditional B is implanted at 15-40 keV at doses in the range of 5×10¹²to 5×10¹³ atoms/cm² to form the shallow NMOS APT suppression layer.

In step 950 carbon is optionally implanted to form a deep carbon implantlayer that is positioned between the NMOS screen layer and the NMOS APTlayer. Embodiments of DDC transistors having a deep carbon implant layerhave been described previously with reference to FIGS. 7 and 8. In oneembodiment, carbon can be implanted at 20-60 keV at doses in the rangeof 1×10¹⁴ to 1×10¹⁵ atoms/cm² to form the deep carbon implant layer. Instep 955, the NMOS screen layer is formed, which is followed by a 900°C.-1250° C. RTP/laser well anneal in step 960 and removal of the NMOSmask in step 965. In one embodiment, B is implanted at 0.5 to 10 keV atdoses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the NMOS screenlayer. Typically the implant conditions for the NMOS screen layer areselected such that the NMOS screen layer is formed within the carbondoped silicon substrate formed in step 905 (if present), and positionedabove the deep carbon implant layer formed in step 950. Since the deepcarbon implant layer protects the NMOS screen layer from interstitialsgenerated below the screen layer, it is typically positioned eitherclose to the NMOS screen layer or above the source of interstitialsbelow the screen layer. In alternative embodiments, fluorine can beimplanted instead of carbon to form the deep implant layer. The use offluorine instead of carbon can be advantageous because fluorine can befully activated with a normal spike anneal, while carbon may only bepartially activated. In one embodiment, shown in step 970, a blanketepitaxial layer of substantially undoped silicon is grown, such that thesubstantially undoped silicon layer is formed over the screen layers ofboth the NMOS and PMOS transistors. In certain other embodiments, shownin steps 975 and 980, respectively, an intermediate blanket epitaxialcarbon doped silicon layer can be grown followed by a blanket epitaxiallayer of substantially undoped silicon. Typically thin (about 5-10nanometers or so), the carbon doped silicon layer formed at step 975 canact to reduce diffusion of dopants from the screen layer into thesubstantially undoped epitaxial layer and it can also consume unwantedsilicon interstitials generated above the screen layer and to furtherreduce boron diffusion in the device structure. In one embodiment, theblanket epitaxial layer grown in step 980 can have a thickness that isapproximately in the range of 5-40 nanometers. Embodiments of DDCtransistors having an in-situ epitaxial carbon doped silicon layerpositioned above the screen layer have been described previously withreference to FIGS. 5-8.

Various embodiments of the process 900 can include some but not all ofthe process steps for forming one or more of the carbon doped siliconlayers described above, i.e. steps 905, 950, and 975. In one suchembodiment, step 905 is performed so that the DDC transistors are formedin a silicon substrate with carbon dopants, while steps 950 and 975 areperformed to form the deep carbon implant layer below the screen layerand the thin in-situ carbon doped silicon layer above the screen layer,respectively. In alternative embodiments, only one of the steps 905,950, and 975 are performed such that only one carbon doping is used tolimit the diffusion of screen layer dopants. In other embodiments, allthree of these steps are performed, such that three carbon dopings areused to limit the diffusion of screen layer dopants.

FIG. 10 illustrates several embodiments of a process 1000 where the STIstructures are formed before forming the DDC transistor elements. Theprocess 1000 can use selective epitaxy in place of the blanket epitaxysteps described above with reference to the process 900 of FIGURE andcan, therefore, eliminate additional steps for removing the unwantedsilicon growth that would otherwise be formed over exposed dielectricstructures, e.g. polysilicon that would be formed over STI elements ifblanket epitaxy processing was utilized after STI formation. In oneembodiment of the process 1000, as shown in step 1005, carbon dopedsilicon is in-situ grown as a blanket epitaxial layer, forming a carbondoped silicon substrate into which the DDC transistors can subsequentlybe fabricated. In an alternative embodiment, the substrate level carbondoped silicon growth step can be omitted and the DDC transistors can beformed in the silicon substrate or in a well in the silicon substrate.In one embodiment, the process conditions for forming the carbon dopedsilicon substrate in step 1005 are similar to the process conditionsdescribed above with reference to step 905 of FIG. 9.

In step 1007, the STI structures are optionally formed for an embodimentusing an STI first process flow, thereby defining the areas where theNMOS and PMOS DDC transistors are to be formed. In an alternativeembodiment using an STI last process flow, step 1007 can be omitted andSTI structures are not formed at this stage of the process. In step1010, a PMOS mask is lithographically patterned on the wafer, which isthen used in step 1015 to form the PMOS well. In one embodiment,phosphorus (P) is implanted at 200-400 keV, at doses in the range of1×10¹³ to 5×10¹³ atoms/cm² to form the PMOS well. In steps 1020 and1025, respectively, the PMOS APT suppression layer and the PMOS screenlayer are formed. In one embodiment, arsenic (As) is implanted at 50-200keV at doses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the PMOSAPT suppression layer and antimony (Sb) is implanted at 10-50 keV atdoses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the PMOS screenlayer. The PMOS mask is removed at step 1030 and an NMOS mask is formedat step 1035. In step 1040, the NMOS mask is used to form the NMOS well.In one embodiment, boron (B) is implanted at approximately 100-250 keV,at doses in the range of 1×10¹³ to 5×10¹³ atoms/cm² to form the NMOSwell. In step 1045, the NMOS APT suppression layer is implanted in theNMOS well. In one embodiment, additional B is implanted at 15-40 keV atdoses in the range of 5×10¹² to 5×10¹³ atoms/cm² to form the shallowNMOS APT suppression layer.

In step 1050, an optional deep carbon implant can be performed toimplant carbon above the APT suppression layer, followed by step 1055that forms the NMOS screen layer above the carbon implant region. Thedeep carbon implant layer formed in step 1050 can limit the diffusion ofNMOS screen layer dopants by trapping interstitials generated below thescreen layer. The deep carbon implant layer may be used in addition toor in lieu of the carbon doped silicon substrate formed in step 1005.Typically, either the deep carbon implant layer or the carbon dopedsilicon substrate is used in a particular embodiment, with the deepcarbon implant layer being used when the DDC transistors are formed in asilicon substrate instead of the carbon doped silicon substrate. Thus,the step 1050 for forming the deep carbon implant layer can be omittedin certain embodiments of the process 1000. Step 1050 can result in adeep carbon implant that is positioned between the APT layer and thescreen layer for the NMOS transistor, such that the deep carbon implantcan limit the diffusion of NMOS screen layer dopants (such as boron). Inone embodiment, carbon is implanted at 20-60 keV at concentrations inthe range of 1×10¹⁴ to 1×10¹⁵ to form the deep carbon implant layer. Inone embodiment, B is implanted at 0.5 to 10 keV at concentrations in therange of 5×10¹² to 5×10¹³ to form the NMOS screen layer. Typically, theimplant conditions for the NMOS screen layer are selected such that theNMOS screen layer is formed within the carbon doped silicon substrateformed in step 1005 and positioned above the deep carbon implant layerformed in step 1050. Since the deep carbon implant layer protects theNMOS screen layer from interstitials generated below the screen layer,it is typically positioned either close to the NMOS screen layer orabove the source of interstitials below the screen layer (e.g., an areawhere the lattice structure may be damaged). In alternative embodiments,fluorine can be implanted instead of carbon to form the deep implantlayer. The use of fluorine instead of carbon can be advantageous becausefluorine can be fully activated with a normal spike anneal, while carbonmay only be partially activated. In step 1060, a 900° C.-1250° C.RTP/laser well anneal is performed.

In step 1065, the NMOS mask is removed and, in step 1068, an optionalhardmask may be formed. The hardmask formed in step 1068 can be used todefine the regions of the NMOS and PMOS transistors such that the STIislands are masked off in process embodiments that use an STI firstprocess flow so that subsequent steps that form selective epitaxiallayers for the NMOS and PMOS transistors do not form polysilicon overthe STI islands. Moreover, the hardmask of step 1068 can be used todefine transistors having a predetermined threshold voltage such thatthe subsequent steps that form epitaxial layers for the transistors canform selective epitaxial layers of different thicknesses for transistorshaving different threshold voltages. For example, epitaxial layershaving different thicknesses can be formed for LVt transistors having alow threshold voltage and HVt transistors having a high thresholdvoltage, and different hardmasks can be formed to define the LVt and HVttransistor areas. In an alternative embodiment, different hardmasks canbe formed to define the NMOS and PMOS transistor areas, permitting theuse of different epitaxial layers for the NMOS and PMOS transistors. Forexample, a NMOS hardmask can be used to form carbon doped siliconepitaxial layers for the NMOS transistors and a PMOS hardmask can beused to form a substantially undoped epitaxial layer for the PMOStransistor so the PMOS transistors have no carbon dopants.

In one embodiment of the process 1000, shown in step 1070, a selectiveepitaxial layer of substantially undoped silicon is grown over theregions where the NMOS and PMOS transistors are to be formed. In analternative embodiment, shown in steps 1075 and 1080 respectively, anintermediate selective epitaxial carbon doped silicon layer can be grownfollowed by a selective epitaxial layer of substantially undopedsilicon. Typically thin (about 5-nanometers or so), the carbon dopedsilicon epitaxial layer formed at step 1075 can act to reduce diffusionof dopants from the screen layer into the substantially undopedepitaxial layer and it can also consume unwanted silicon interstitialsto further reduce boron diffusion in the device structure. In oneembodiment, the selective epitaxial layers grown in steps 1070 and 1074can have a thickness that is approximately in the range of 5-40nanometers. In certain embodiments, a hardmask can be formed in step1068 to support the subsequent selective epitaxial deposition steps. Forexample, a hardmask defining the PMOS transistor regions can be used toperform step 1070 for the PMOS transistors and a different hardmaskdefining the NMOS transistor regions can be used to perform steps 1075and 1080 for the NMOS transistor regions.

In one embodiment of the process 1000, the carbon implant layer and thecarbon doped silicon substrate is formed only for the NMOS transistorswhile PMOS transistors are kept free of carbon. Such an embodiment canbe advantageously used if low diffusivity dopant species are used toform the PMOS screen layer such that the dopant profile of the PMOSscreen layer can be maintained without using carbon. Eliminating carbonin the PMOS transistor can be beneficial because the presence of carbondopants can reduce the charge carrier mobility and may have an effect ontransistor electrical characteristics. In order to accommodate this, theoptional step 1005 is omitted such that the corresponding carbon dopedsilicon substrate is not formed. A selective silicon etch for the NMOStransistor regions is performed (step 1072) prior to forming the thinin-situ carbon doped silicon selective epitaxial layer (step 1073) forthe NMOS transistors. The purpose of the selective etch for the NMOStransistors is to recess the silicon region of the NMOS transistors suchthat, after deposition of the carbon doped silicon substrate in step1005, the NMOS transistor regions can have substantially the same stepheight as the PMOS transistor regions. Subsequently, a substantiallyundoped silicon epitaxial layer is grown as selective epitaxial layer instep 1074 such that a selective epitaxial layer is formed over thescreen layers of both the NMOS and PMOS transistors.

In step 1085, a low temperature STI process step is performed to formSTI structures for a process embodiment using an STI last process flow.In step 1090, remaining elements of the NMOS and PMOS transistors areformed, such as gate structures, source/drain implants, etc.

FIG. 11 illustrates a process 1100, where STI is processed after thescreen and channel layers of the DDC transistors have been formed. Theprocess flow 1100 utilizes additional steps to allow the carbon speciesto be limited to the NMOS device. In step 1110, a PMOS mask islithographically patterned on a wafer, which is then used in step 1115to form a PMOS well. In one embodiment, phosphorous is implanted at200-400 keV to form the PMOS well. The PMOS APT suppression layer andthe PMOS screen layer are formed in steps 1120 and 1125, respectively.In one embodiment, arsenic (As) can be implanted at 50-200 keV to formthe PMOS APT suppression layer and antimony (Sb) can be implanted at10-50 keV to form the PMOS screen layer. In steps 1130 and 1135,respectively, the PMOS mask is removed and an NMOS hard mask is formed.

Referring to FIG. 11, in step 1140, a selective silicon etch isperformed in regions where the NMOS transistors are to be formed. Thepurpose of the selective silicon etch is to recess the silicon region ofthe NMOS transistors such that, after subsequent deposition of selectiveepitaxial layers for the NMOS transistors, the NMOS transistors regionscan have substantially similar height as the PMOS transistor regions. Inone embodiment, the selective silicon etch step 1140 is performed beforethe NMOS well implant and the NMOS screen implant in steps 1145 and1150, respectively. In an alternative embodiment, the selective siliconetch step 1140 is performed after step 1145 and 1150. In one embodiment,Boron (B) is implanted at 100-250 keV to form the NMOS well andadditional B is implanted at 15-40 keV to form a shallow NMOS APTsuppression layer. If the depth of the selective silicon etchback issmall compared to the depth of the NMOS well and NMOS APT suppressionlayers, then the NMOS well and NMOS APT suppression layer implantconditions are similar for the process embodiment that performs the NMOSselective well etch before step 1145, as compared to the embodiment thatperforms the NMOS selective well etch after step 1150. For example,similar implant conditions for the two embodiments are performed if thedepth of the selective well etch is about 30 nm. Alternatively, theprocess embodiment that performs the NMOS selective well etch beforestep 1145 can use a lower implant energy for the NMOS well and NMOS APTsuppression implants, as compared to the embodiment that performs theNMOS selective well etch after step 1150. In step 1155, NMOS selectiveepitaxial steps are performed to form the layers for the NMOStransistors. In accordance with various embodiments, these epitaxialsteps can form an NMOS transistor stack that includes (a) a firstselective epitaxial layer of carbon doped silicon, followed by a secondselective epitaxial layer of silicon doped with carbon and NMOS screenlayer dopants (such as boron), followed by a third selective epitaxiallayer of thin carbon doped silicon that is formed above the secondlayer; or (b) a selective epitaxial layer of silicon doped with carbonand NMOS screen layer dopants to form a doped substrate layer; or (c) aselective epitaxial layer of carbon doped silicon to form a carbon dopedsubstrate in which NMOS screen layer dopants are subsequently implanted.

In step 1160, a NMOS transistor threshold implant can be optionallyperformed, if the NMOS transistors have a threshold set region. In step1170, the NMOS mask is removed, and in step 1175 various thermalprocessing steps can be performed, including at step 1175 a 500° C.-800°C. SPE or a 900° C.-1250° C. RTP well anneal. In step 1180, a blanketepitaxial layer of substantially undoped silicon is formed such that theepitaxial layer is formed over the screen layers of both the NMOS andPMOS transistors. In one embodiment, the blanket epitaxial layer canhave a thickness that is approximately in the range of 5-40 nanometers.After formation of the DDC transistor elements (such as the well implantlayers and the substantially undoped channel layer described above), alow temperature STI formation is performed at step 1185 followed by gateformation at step 1190. Remaining transistor process modules areperformed to complete the formation of the DDC transistor.

Transistors created according to the foregoing embodiments, structures,and processes can have a reduced threshold voltage mismatch arising fromdiffusion mediated dopant variations as compared to conventional MOSanalog or digital transistors. This is particularly important fortransistor circuits that rely on closely matched transistors for optimaloperation, including differential matching circuits, analog amplifyingcircuits, and many digital circuits in widespread use such as SRAMcells. Variation can be even further reduced by adoption of structuressuch as a screen layer, an undoped channel, or a Vt set layer asdescribed herein to further effectively increase headroom which thedevices have to operate. This allows high-bandwidth electronic deviceswith improved sensitivity and performance, but still having reducedpower consumption.

The present disclosure discusses building the screen and channel ofadvanced transistors such as a deeply depleted channel (DDC) typetransistor. However, the methods and techniques described above can alsobe used by one skilled in the art to improve the securement of dopantprofiles in other transistor types or transistor features such asshallow lightly doped drains (LDD) and S/D regions in advancedtransistors.

Although the present disclosure has been described in detail withreference to a particular embodiment, it should be understood thatvarious other changes, substitutions, and alterations may be made hereinwithout departing from the spirit and scope of the appended claims.Numerous other changes, substitutions, variations, alterations, andmodifications may be ascertained by those skilled in the art and it isintended that the present disclosure encompass all such changes,substitutions, variations, alterations, and modifications.

What is claimed is:
 1. A method for forming a plurality of FETs in asubstrate, comprising: forming at least one PMOS FET; and forming atleast one NMOS FET, the forming at least one NMOS FET includes:implanting a dopant to form an NMOS anti-punchthrough layer; implantinga dopant to form an NMOS screen layer; forming a carbon-containingregion above the NMOS screen layer; forming a diffusion-inhibitingregion below the NMOS screen layer using a diffusion-inhibiting materialimplant, wherein the carbon-containing region and thediffusion-inhibiting region are operable to substantially limitdiffusion of the NMOS screen layer dopants; annealing using a lowthermal budget anneal; and depositing a substantially undoped epitaxialsilicon layer on the carbon-containing region; and forming trenchisolation structures to electrically isolate the plurality of FETs fromone another.
 2. The method of claim 1, wherein the diffusion-inhibitingregion comprises a material selected from the group consisting of carbonand fluorine.
 3. The method of claim 2, wherein the carbon is formedusing ion implantation.
 4. The method of claim 1, wherein annealingincludes using solid phase epitaxy at a temperature of between 500 and800 degrees Celsius.
 5. The method of claim 1, wherein annealingincludes using a rapid thermal anneal at a temperature of between 900and 1250 degrees Celsius.
 6. The method of claim 1, wherein depositing asubstantially undoped epitaxial silicon layer includes using selectiveepitaxial growth.
 7. The method of claim 1, wherein thecarbon-containing region is formed using doped epitaxial growth.
 8. Amethod for forming a plurality of transistor devices in a substrate, thetransistor devices each having a defined threshold voltage, the methodcomprising: forming a PMOS field effect transistor (FET) in a firstdoped well of the substrate, the PMOS FET having a source and a drain,wherein the forming the PMOS FET includes: implanting dopants in thefirst doped well to form a PMOS anti-punchthrough layer; and implantingdopants in the first doped well to form a PMOS screen layer above thePMOS anti-punchthrough layer, the PMOS screen layer being positionedlaterally between eventual positions of the source and the drain;forming an NMOS field effect transistor (FET) in a second doped well ofthe substrate, the NMOS FET having a source and a drain, wherein formingthe NMOS FET includes: implanting dopants in the first doped well toform an NMOS anti-punchthrough layer; forming an NMOS screen layer abovethe NMOS anti-punchthrough layer, the NMOS screen layer being positionedlaterally between eventual positions of the source and the drain;forming an epitaxial carbon-containing silicon layer positioned abovethe NMOS screen layer, the epitaxial carbon-containing silicon layerbeing formed as a selective epitaxial layer; and performing an anneal;and forming a plurality of shallow trench isolation structures to definea plurality of transistor regions.
 9. The method of claim 8, whereinperforming an anneal includes using solid phase epitaxy at a temperatureof between 500 and 800 degrees Celsius.
 10. The method of claim 8,wherein performing an anneal includes using rapid thermal anneal at atemperature of between 900 and 1250 degrees Celsius.
 11. The method ofclaim 8, further including forming an epitaxial silicon material overthe epitaxial carbon-containing silicon layer.
 12. The method of claim11, wherein forming an epitaxial silicon material includes forming ablanket epitaxial silicon layer over each FET.
 13. A method for formingan NMOS field effect transistor (FET) in a doped well of a substrate,the NMOS FET having a source and a drain, comprising: forming anepitaxial carbon-containing silicon layer in the doped well; implantingdopants to form an NMOS anti-punchthrough layer positioned below thecarbon-containing silicon layer; implanting dopants in the epitaxialcarbon-containing silicon layer to form an NMOS screen layer above theanti-punchthrough layer, the NMOS screen layer being positionedlaterally between eventual positions of the source and the drain;annealing the substrate; implanting dopants in the epitaxialcarbon-containing silicon layer to form a threshold voltage set layerabove the NMOS screen layer; following implanting of all dopants,depositing a substantially undoped epitaxial silicon material on theepitaxial carbon-containing silicon layer; and forming a gate structureon the epitaxial silicon material.
 14. The method of claim 13, whereinannealing the substrate includes using solid phase epitaxy at atemperature of between 500 and 800 degrees Celsius.
 15. The method ofclaim 13, wherein annealing the substrate includes using rapid thermalanneal at a temperature of between 900 and 1250 degrees Celsius.
 16. Themethod of claim 13, wherein the epitaxial silicon material is a blanketepitaxial layer over multiple FETs.
 17. The method of claim 13, whereina shallow trench isolation is formed in the substrate.